module top_module (
    input clk,
    input x,
    output z
); 

    wire	Q1;
    wire	Q2;
    wire	Q3;
    wire	Q2n;
    wire	Q3n;
    wire	D1;
    wire	D2;
    wire	D3;
    
    assign D1 = x ^ Q1;
    assign D2 = x && Q2n;
    assign D3 = x || Q3n;
    assign z = ~(Q1 || Q2 || Q3); 
    assign Q2n = ~Q2;
    assign Q3n = ~Q3;
    
    always @(posedge clk) begin
        Q1 <= D1;
        Q2 <= D2;
        Q3 <= D3;
    end
    
endmodule
